Careers

VLSI :

Provide appropriate designations

Design Verification Engineer:

Junior level:

  • 0 to 1 years of experience in Verification with B.E/B.Tech/M.E/M.Tech.

  • Knowledge on Verilog/SystemVerilog/UVM/OVM.

  • Knowledge of atleast one scripting language like Python, Perl, Shell, TCL

  • Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams


Mid-level level:

  • 2 to 4 years of experience in Verification with B.E/B.Tech/M.E/M.Tech.

  • Good knowledge on Verilog/System Verilog/UVM/OVM.

  • Knowledge of at least one scripting language like Python, Perl, Shell, TCL

  • Knowledge of at least one industry standard protocols like Ethernet, PCIe, USB, SATA, NVMe, AMBA, ARM, RISC CPUs etc.,

  • Able to work on functional coverage modelling and Code coverage analysis.

  • Experience in GLS will be added advantage.

  • Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams


Senior level:

  • 5 to 7 years of experience in Verification with B.E/B.Tech/M.E/M.Tech.

  • Good knowledge on Verilog/SystemVerilog/UVM/OVM.

  • Knowledge of at least one scripting language like Python, Perl, Shell, TCL

  • Knowledge of at least one industry standard protocols like Ethernet, PCIe, USB, SATA, NVMe, AMBA, ARM, RISC CPUs etc.,

  • Good RTL debugging skills.

  • Expertise in independently creating detailed test plan with well-defined functional coverage goals.

  • Hands on experience on GLS sims with SV UVM based env.

  • DV planning and risk mitigation

  • Communicate with all stakeholders (design, PD and HQ) for scheduled alignment, risk assessment and other responsibilities

  • Support post silicon team, DFT and PD team for characterization, vector generation and power analysis

Design Engineer:

  • 2+ years of experience in the field of front-end design, synthesis and STA

  • In-depth knowledge of synthesis, static timing analysis and constraints development

  • In-depth knowledge of RTL design fundamentals

  • In-depth knowledge of Verilog and System-Verilog

  • In-depth knowledge of front-end tools (Verilog compilers/simulators, linters, clock-domain crossing checkers, RTL synthesis, STA)

  • DFT knowledge is a plus

  • Good knowledge of scripting languages such as Perl, Tcl and Python

  • Strong communication and presentation skills

DFT:


Junior level ( 2+ years)

    • Experience on DFT logic insertion using Mentor Tessent or SNPS Testmax Hierarchical flow.

    • Experience on DFT logic verification and ATPG


Mid level ( 5+ years)

  • Experience on Top-Level & Block-Level DFT verification covering Mbist , tap , BSD, Stuck at fault , transition fault. In both Zero delay and with timing

  • Experience on DFT logic insertion using Mentor Tessent Hierarchical flow.

Senior Level( 8+ years)

  • Experience on DFT strategy definition for block and top level covering Mbist , scan compression , BSD, tap controller , OCC

  • 2+ years of experience in the field of front-end design, synthesis and STA

  • In-depth knowledge of synthesis, static timing analysis and constraints development

  • In-depth knowledge of RTL design fundamentals

  • In-depth knowledge of Verilog and System-Verilog

  • In-depth knowledge of front-end tools (Verilog compilers/simulators, linters, clock-domain crossing checkers, RTL synthesis, STA)

  • DFT knowledge is a plus

  • Good knowledge of scripting languages such as Perl, Tcl and Python

  • Strong communication and presentation skills ·

  • Knowledge and experience on Top-Level & Block-Level Insertion and Verification of DFT Logic.

  • Experience with DCNXT / Fusion Compiler DFT Flow on top level and block level

  • Experience on timing constraints generation and debug for DFT modes.

Physical design:

  • 3-6 years’ experience in complex ASIC Design projects.

  • Have in depth knowledge of entire physical design process from floorplan till GDS generation

  • Good Exposure to Physical Verification Process

  • Hands on experience in leading PnR tools Synopsys ICC / Cadence Encounter etc

  • Experience in low power designs and handling congestion or timing critical tiles will be preferred

  • Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl / Python etc

  • Must have good communication & problem - solving skills.

  • Should be able to handle PnR tasks with minimal supervision Bachelor / master’s degree in Electronics Engineering