DIGITAL VERIFICATION Services

Verification Services

Delanceytech team has Vast expertise in end-to-end system testing, building verification components, constrained-random testing. Providing our Service to engage at any stage of the semiconductor front end design process. Our team can implement verification of complex SoC’s and IP’s from scratch level by using latest methodologies such as SV-UVM,OVM, UPF and achieving 100% functional and code coverage.

Verification is one of the key issues in IC design and development impacting product schedules and timelines. We offer a wide range of ASIC verification services which help customers to achieve working silicon the first time.

Rapid progresses in silicon technology offer excellent possibilities in including digital / analog cells, embedded processors, high speed IO, memories, in-house / 3rd-party IP and more onto a single device. Our verification resources understand the challenges involved in such designs and work closely with customers to offer specific solutions that help in achieving the required capability on a complete chip.

Design Verification Process

Identification and preparation:

During the development stage of a specification, the identification of verification activity is done parallel. This enables the designer to make sure that the specification is verifiable. So a test engineer can start detailed test plan and procedures. Any changes in the specification should be communicated.

  • Identifying the best approach to conduct verification, define measurement methods, required resources, tools, and facilities.

  • The completed verification plan will be reviewed with the design team to identify issues before finalizing the plan.

Planning:

  • Planning for verification is a concurrent activity with core and development teams. This occurs throughout the project life cycle. This will be updated as and when any changes are made to design inputs.

  • During this phase, the software or system under test shall be documented in scope.

  • Preliminary test plan and test plan refinement are made at this stage. Test plan captures the critical milestone reducing the project risk.

  • Tools, test environment, development strategy and identifying the requirements through inspection or analysis.

Developing:

  • The test case development will coincide with SDLC methodology implemented by a project team. A variety of test methods are identified during this stage.

  • The design inputs must be developed including simplest verification activities which are unambiguous and verifiable.

  • Verification time shall be reduced when similar concepts are conducted in sequence. Even the output of one test can be used as input for subsequent tests.

  • Tractability links are created between test cases and corresponding design inputs, to ensure that all the requirements are tested and the design output meets the design inputs.

Execution:

  • The test procedures created during the development phase is executed in accordance with the test plan, strictly following them in verification activity.

  • If any invalid results occur or if any procedures required modification, it is important to document the changes and get proper approval.

  • Any issues are identified and logged as a defect at this stage.

  • Tractability matrix is created to verify that all the design input identified in the verification test plan has been tested and determine the pass ratio.

Reports:

  • This activity is performed at the end of each phase of verification execution.

  • The design verification report gives the detailed summary of verification results which includes the configuration management, test results for each type of testing and issues found during the verification activity.

  • Design verification traceability report is created between requirements and corresponding test results to verify all the requirements have been tested and provided with appropriate results.

  • Any non-conformance will be documented and appropriately addressed.

  • Reviews are done upon the completion of design verification activity and are approved respectively.

Design Validation Process

  • Some of the designs may be validated by comparing with similar equipment performing similar purpose. This method is particularly relevant for validating configuration changes for existing infrastructure, or standard designs that are to be incorporated in a new system or application.

  • Demonstration and/or inspection may be used to validate requirements and other functionality of the product.

  • Analyzing the design can be done such as mathematical modeling, a simulation which can recreate the required functionality.

  • Tests are performed on the final design that validates the ability of the system to operate as per the specified design.

  • Test plan, execution, and results should be documented and maintained as a part of design records. Thus, Validation is a collection of the results of all validation activities.

  • When equivalent products are used in the final design validation, the manufacturer must document the similarity and if any difference from initial production.