Physical Design

Physical Design Services

Delanceytech provides a complete suite of physical design services focused on high-performance designs, low power designs. This include synthesis, place and route, physical verification and final STA signoff. Based on our experience, commitment and motivation, our number one goal is to make sure our customer’s product reaches the market much faster.

Physical_Design

Physical design refers to the backend design cycle. If there’s just one aspect that distinguishes the backend design from frontend design, then it would be- delay. Frontend design, while being cognizant of the logic delays and speed, largely ignores it for majority part of the RTL coding and verification. While, on the other hand, physical design sees real delay right from the very beginning.

Physical design flow is further sub-divided into the following:

  • Synthesis

  • STA

  • Physical Design and Timing Verification

Synthesis

  • RTL -> Netlist Synthesis set-up

  • Constrain development to convert the behavioral or dataflow code into real physical standard cell gates.

  • Optimization of GATE count thereby minimizing latency and power consumption.

STA

  • STA flow Setup

Identifying timing constraints and exception handling.

  • Closure of timing for FAST and SLOW corners with respect to best case and worst case scenarios.

  • Timing ECOs for critical paths.

  • Signal integrity analysis.

  • Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow.


Physical Verification

  • DRC (Design Rule Checks)

  • LVS (Layout versus Schematic)

  • Electromigration

  • Electro-static discharge violations (ESD)

  • Antenna violations

  • Pattern Match (PM) violations, Shorts, Opens, Floating nets etc.


Physical Design and Timing Verification

While logic verification ensures correct functionality, physical verification ensures correct layout. There’s been an increase in Physical Verification checks which includes-

  • DRC (Design Rule Checks)

  • LVS (Layout versus Schematic)

  • Electro migration

  • Electro-static discharge violations (ESD)

  • Antenna violations

  • Pattern Match (PM) violations, Shorts, Opens, Floating nets etc.

It is important to track these violations in parallel with the Place and Route flow to avoid any surprises just days before tape-out. Timing Verification verifies that the chip runs at the specified frequency by ensuring setup and hold is met for all timing paths in the design.

Our Physical design process include:

  • Physical Design and Verification flow setup

  • Top level and block level Floor planning

  • Power planning

  • Placement & Routing(PnR) and its Optimization

  • CTS

  • Power optimization and IR Drop Analysis.