Our Services
The cost of design, manufacture and test of modern-day VLSI chips is forcing companies to always innovate and bring out better designs that can make them standout from others and give an edge over competition.
Digital Design
We bring your ideas to life
Digital design services at Delancey provide RTL design services and solutions to our customers in semiconductor industry in the areas of ASIC & FPGA design and SOC integration. Our designers have hands-on experience of the very new technologies, methodologies, languages, and techniques used in the industry.
ASIC Design Services
Micro Architecture
RTL Development
Low power design implementation and checks
SONET/SDH , PCIe, Ethernet, SAS, USB, DDR/LPDDR Subsystems and test chips
Bus protocols like AMBA AXI, AHB, APB protocols
SOC/Sub-system integration
RTL QC Checks LINT, CDC
Timing constrains, Synthesis and STA
UPF, CPF
LEC
FPGA Design Services
FPGA System architecture
Software-hardware partitioning
Defining microarchitecture including FPGA vendor provided IPs, Custom IPs and to be developed modules.
Converting custom requirements to efficient HDL.
Design synthesis and time closure.
Board bring-up for FPGA design and validation using customer software,
protocol analyzers and test equipment’s.
Performance validation of design across supported voltage, temperature corners etc
Digital Verification - ASIC/SOC
Digital Verification
Delancey has strongest team in DV. Our team can execute verification from scratch of SoC’s and IP’s by using latest methodologies such as SV-UVM, and meeting 100% functional and code coverage. Our team has developed few VIP’s
Advanced IP & SoC Verification
SV-UVM Based Constrained - Random Verification
Feature list extraction and Test Bench Development
Low Power Verification – UPF/CPF
Gate Level simulation
VIP Development and Integration
GLS and PAGLS
Good exposure in power estimation/power architecture and power reduction techniques.
UPF flow setup
GLS flow setup with different tools from scratch.
Clean up X propagation and debug
sign-off Gate Level Simulation
Expertise in different safety standards to help verification and certification of safety application specific SoC’s
DFT Services
DFT Planning, Architecture, Flow and Methodology Development.
DFT Implementation which includes, Test Pin-Muxing, SCAN Insertion, LBIST Insertion, Compression Logic Insertion, Boundary Scan Insertion, Memory BIST insertion and IOs.
Automatic Test Pattern Generation (ATPG), ATPG verification.
DFT simulations for zero delay and timing for SCAN, Boundary SCAN, MBIST & LBIST modes
Physical Design
DFT Planning, Architecture, Flow and Methodology Development.
DFT Implementation which includes, Test Pin-Muxing, SCAN Insertion, LBIST Insertion, Compression Logic Insertion, Boundary Scan Insertion, Memory BIST insertion and IOs.
Automatic Test Pattern Generation (ATPG), ATPG verification.
DFT simulations for zero delay and timing for SCAN, Boundary SCAN, MBIST & LBIST modes
Embedded:
· Our team has worked on developing embedded system software for cutting edge SOC modules is to develop a low power and small memory footprint platform without compromising system performance. Also, it requires expertise in handling multi core platforms for various product solutions and migration of 32 bit to 64-bit systems for application porting.
· We have proven expertise in system software and below are our key offerings: -
Embedded solutions with advanced ARM core on various operating systems Linux kernel. RTOS
Device driver development and Firm ware development as well
Porting of middleware for 64-bit processors.
Our team has experience in multimedia and connectivity with respect to mobile/wireless software